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bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 1-4 cell li+ battery smbus charge controller with independent comparator and advanced circuit protection check for samples: bq24707 , bq24707a 1 features description ? smbus host-controlled nmos-nmos the bq24707 and bq24707a are high-efficiency, synchronous buck converter with synchronous battery charger, offering low component programmable 615khz, 750khz, and 885khz count for space-constraint, multi-chemistry battery charging applications. switching frequency ? real time system control on ilim pin to limit smbus controlled input current, charge current, and charge current charge voltage dacs allow for very high regulation accuracies that can be easily programmed by the ? enhanced safety features for over voltage system power management micro-controller. protection, over current protection, battery, inductor, and mosfet short circuit protection the ic uses the internal input current register or external ilim pin to throttle down pwm modulation to ? programmable input current, charge voltage, reduce the charge current. charge current limits C 0.5% charge voltage accuracy up to 19.2v the ic provides an ifault output to alarm if any mosfet fault or input over current occurs. this C 3% charge current accuracy up to 8.128a alarm output allows users to turn off input power C 3% input current accuracy up to 8.064a selectors when the fault occurs. meanwhile, an C 2% 20x adapter current or charge current independent comparator with internal reference is available to monitor input current, output current, or output accuracy output voltage. ? programmable adapter detection and indicator the ic charges one, two, three, or four series li+ cells, and is available in a 20-pin, 3.5 3.5 mm 2 qfn ? independent comparator with internal package. reference ? integrated soft start ? integrated loop compensation ? ac adapter operating range 5v-24v ? 15 a off-state battery discharge current ? 20-pin 3.5 x 3.5 mm 2 qfn package ? bq24707: acok delay default 1.3s ? bq24707a: acok delay default 1.2ms applications ? portable notebook computers, umpc, ultra-thin notebook, and netbook ? personal digital assistant ? handheld terminal ? industrial and medical equipment ? portable equipment 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. ? 2010 C 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 12 3 4 5 6 7 8 9 10 1514 13 12 11 20 19 18 17 16 acn acp cmpout cmpin acok acdet iout sda scl ilim ifault srn srp gnd lodrv regn btst hidrv phase vcc bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. typical application f s = 750khz, i adpt = 4.096a, i chrg = 2.944a, i lim = 4a, v chrg = 12.592v, 90w adapter and 3s2p battery pack see the application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection. figure 1. typical system schematic ordering information ordering number part number ic marking package quantity (tape and reel) bq24707rgrr 3000 bq24707 bq707 20-pin 3.5 x 3.5mm 2 qfn BQ24707RGRT 250 bq24707argrr 3000 bq24707a bq07a 20-pin 3.5 x 3.5mm 2 qfn bq24707argrt 250 comparison table condition bq24707 bq24707a acok default delay 1.3s 1.2ms suggest fully charged battery chargevoltage() setting full scale charge voltage(12.592v for 3s battery) 0v after termination suggest fully charged battery chargecurrent() setting 0a 0a after termination 2 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a vcc regn btst hidrv phase lodrv gnd srp srn q4sis412dn l1 4.7h system c10 10f rsr 10m ? r1 430k r2 66.5k c2 0.1f u1 bq24707 bq24707a c810uf q3sis412dn q5 (batfet) si4435ddy c7 0.047f adapter + rac 10m ? pack + c6 1f host dig i/o smbus +3.3v c4 100p r4 10k r5 10k r7 316k acn acp acdet ilim sda scl acok ifault cmpout cmpin iout ci 2.2f ri2 ? r9 10 r3 10k r8 100k d1 bat54 c910uf c11 10f pack c3 0.1f c5 1f c1 0.1f total csys 220f adapter adc q1 (rbfet)si4435ddy q2 (acfet)si4435ddy powerpad r6 10k controlledby host controlledby host d2rb751v40 if no adapter, and iout is needed, this rail is on +1.5v r10 10k r11 39.2k r12 100k r133.01m c13 0.1f c14 0.1f r1410 r157.5 * *
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) value unit srn, srp, acn, acp, vcc C 0.3 to 30 phase C 2 to 30 voltage range acdet, sda, scl, lodrv, regn, iout, ilim, acok, ifault, cmpin, C 0.3 to 7 v cmpout btst, hidrv C 0.3 to 36 maximum difference voltage srp C srn, acp C acn C 0.5 to 0.5 junction temperature range, t j C 40 to 155 c storage temperature range, t stg C 55 to 155 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to gnd if not specified. currents are positive into, negative out of the specified terminal. consult packaging section of the data book for thermal limitations and considerations of packages. thermal information bq24707/bq24707a thermal metric (1) rgr units 20 pins ja junction-to-ambient thermal resistance 46.8 jt junction-to-top characterization parameter 0.6 c/w jb junction-to-board characterization parameter 15.3 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit srn, srp, acn, acp, vcc 0 24 phase C 2 24 voltage range v acdet, sda, scl, lodrv, regn, iout, ilim, acok, ifault, cmpin, 0 6.5 cmpout btst, hidrv 0 30 maximum difference voltage srp C srn, acp C acn C 0.2 0.2 v junction temperature range, t j 0 125 c storage temperature range, t stg C 55 150 c ? 2010 C 2011, texas instruments incorporated submit documentation feedback 3 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com electrical characteristics 4.5 v v (vcc) 24 v, 0 c t j 125 c, typical values are at t a = 25 c, with respect to gnd (unless otherwise noted) parameter test conditions min typ max unit operating conditions v vcc_op vcc input voltage operating range 4.5 24 v charge voltage regulation v bat_reg_rng bat voltage regulation range 1.024 19.2 v 16.716 16.8 16.884 v chargevoltage() = 0x41a0h C 0.5% 0.5% 12.529 12.592 12.655 v chargevoltage() = 0x3130h C 0.5% 0.5% v bat_reg_acc charge voltage regulation accuracy 8.350 8.4 8.450 v chargevoltage() = 0x20d0h C 0.6% 0.6% 4.163 4.192 4.221 v chargevoltage() = 0x1060h C 0.7% 0.7% charge current regulation v ireg_chg_rng charge current regulation differential voltage range v ireg_chg = v srp - v srn 0 81.28 mv 3973 4096 4219 ma chargecurrent() = 0x1000h C 3% 3% 1946 2048 2150 ma chargecurrent() = 0x0800h C 5% 5% 410 512 614 ma charge current regulation accuracy 10m ? current i chrg_reg_acc chargecurrent() = 0x0200h sensing resistor C 20% 20% 172 256 340 ma chargecurrent() = 0x0100h C 33% 33% 64 128 192 ma chargecurrent() = 0x0080h C 50% 50% input current regulation v ireg_dpm_rng input current regulation differential voltage range v ireg_dpm = v acp C v acn 0 80.64 mv 3973 4096 4219 ma inputcurrent() = 0x1000h C 3% 3% 1946 2048 2150 ma inputcurrent() = 0x0800h C 5% 5% input current regulation accuracy 10m ? current i dpm_reg_acc sensing resistor 870 1024 1178 ma inputcurrent() = 0x0400h C 15% 15% 384 512 640 ma inputcurrent() = 0x0200h C 25% 25% input current or charge current sense amplifier v acp/n_op input common mode range voltage on acp/acn 4.5 24 v v srp/n_op output common mode range voltage on srp/srn 0 19.2 v v iout iout output voltage range 0 1.6 v i iout iout output current 0 1 ma a iout current sense amplifier gain v (icout) /v (srp-srn) or v (acp-acn) 20 v/v v (srp-srn) or v (acp-acn) = 40.96mv C 2% 2% v (srp-srn) or v (acp-acn) = 20.48mv C 4% 4% v (srp-srn) or v (acp-acn) = 10.24mv C 15% 15% v iout_acc current sense output accuracy v (srp-srn) or v (acp-acn) = 5.12mv C 20% 20% v (srp-srn) or v (acp-acn) = 2.56mv C 33% 33% v (srp-srn) or v (acp-acn) = 1.28mv C 50% 50% c iout_max maximum output load capacitance for stability with 0 to 1ma load 100 pf regn regulator v regn_reg regn regulator voltage v vcc > 6.5v, v acdet > 0.6v (0-55ma load) 5.5 6 6.5 v i regn_lim v regn = 0v, v vcc > uvlo charge enabled and not in tshut 65 80 regn current limit ma i regn_lim_tshut v regn = 0v, v vcc > uvlo charge disabled or in tshut 7 16 c regn regn output capacitor required for stability i load = 100 a to 65ma 1 f 4 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 electrical characteristics (continued) 4.5 v v (vcc) 24 v, 0 c t j 125 c, typical values are at t a = 25 c, with respect to gnd (unless otherwise noted) parameter test conditions min typ max unit input undervoltage lock-out comparator (uvlo) v uvlo input under voltage rising threshold v vcc rising 3.5 3.75 4 v v uvlo_hys input under voltage falling hysteresis v vcc falling 340 mv fast dpm comparator (fast_dpm) fast dpm comparator stop charging rising threshold 108% v fast_dpm with respect to input current limit, voltage across input sense resistor rising edge (specified by design) quiescent current total battery leakage current to i srn + i srp +i phase + i bat v vcc < v bat = 16.8v, t j = 0 to 85 c 15 a i vcc + i acp + i acn v vcc > v uvlo , v acdet > 0.6v, charge disabled, i standby standby quiescent current, i vcc + i acp + i acn 0.5 1 ma t j = 0 to 85 c adapter bias current during charge, v vcc > v uvlo , v acdet > 2.4v, i ac_nosw 1.5 3 ma i vcc + i acp + i acn charge enabled, no switching, t j = 0 to 85 c adapter bias current during charge, v vcc > v uvlo , v acdet > 2.4v, i ac_sw 10 ma i vcc + i acp + i acn charge enabled, switching, mosfet sis412dn acok comparator v acok_fall acok falling threshold v vcc > v uvlo , v acdet rising 2.376 2.4 2.424 v v acok_rise_hys acok rising hysteresis v vcc > v uvlo , v acdet falling 35 55 75 mv v vcc > v uvlo , v acdet rising above 2.4v, 0.9 1.3 1.7 s chargeoption() bit [15] = 0 (default), (bq24707 only) v vcc > v uvlo , v acdet rising above 2.4v, t acok_fall_deg acok falling deglitch (specified by design) 0.8 1.2 2 ms chargeoption() bit [15] = 0 (default), (bq24707a only) v vcc > v uvlo , v acdet rising above 2.4v, 10 50 s chargeoption() bit [15] = 1 v wakeup_rise wakeup detect rising threshold v vcc > v uvlo , v acdet rising 0.57 0.8 v v wakeup_fall wakeup detect falling threshold v vcc > v uvlo , v acdet falling 0.3 0.51 v vcc to srn comparator (vcc_srn) v vcc-srn_fall vcc-srn falling threshold v vcc falling towards v srn 70 125 180 mv v vcc-srn _rhys vcc-srn rising hysteresis v vcc rising above v srn 70 120 170 mv high side ifault comparator (ifault_hi) (1) chargeoption() bit [8:7] = 00 200 300 450 chargeoption() bit [8:7] = 01 330 500 700 v ifault_hi_rise acp to phase rising threshold mv chargeoption() bit [8:7] = 10 (default) 450 700 1000 chargeoption() bit [8:7] = 11 600 900 1250 low side ifault comparator (ifault_low) v ifault_low_rise phase to gnd rising threshold 40 110 160 mv input over-current comparator (acoc) (1) chargeoption() bit [2:1] = 01 120% 133% 145% adapter over current rising threshold with respect to v acoc input current limit, voltage across input sense resistor chargeoption() bit [2:1] = 10 (default) 150% 166% 180% rising edge chargeoption() bit [2:1] = 11 200% 222% 240% chargeoption() bit [2:1] = 01 (133%), v acoc_min min acoc threshold clamp voltage 40 45 50 mv inputcurrent() = 0x0400h (10.24mv) chargeoption() bit [2:1] = 11 (222%), v acoc_max max acoc threshold clamp voltage 140 150 160 mv inputcurrent() = 0x1f80h (80.64mv) t acoc_deg acoc deglitch time (specified by design) voltage across input sense resistor rising to disable charge 1.7 2.5 3.3 ms bat over-voltage comparator (bat_ovp) v ovp_rise over voltage rising threshold as percentage of v srn rising 103% 104% 106% v bat_reg v ovp_fall over voltage falling threshold as percentage of v srn falling 102% v bat_reg charge overcurrent comparator (chg_ocp) chargecurrent() = 0x0xxxh 54 60 66 mv charge over current rising threshold, measure voltage v ocp_rise chargecurrent() = 0x1000h C 0x17c0h 80 90 100 mv drop across current sensing resistor chargecurrent() = 0x1800 h C 0x1fc0h 110 120 130 mv (1) user can adjust threshold via smbus chargeoption() reg0x12. ? 2010 C 2011, texas instruments incorporated submit documentation feedback 5 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com electrical characteristics (continued) 4.5 v v (vcc) 24 v, 0 c t j 125 c, typical values are at t a = 25 c, with respect to gnd (unless otherwise noted) parameter test conditions min typ max unit charge under-current comparator (chg_ucp) v ucp_fall charge under current falling threshold v srp falling towards v srn 1 5 9 mv light load comparator (light_load) v ll_fall light load falling threshold measure voltage drop across current sensing resistor 1.25 mv v ll_rise_hyst light load rising hysteresis measure voltage drop across current sensing resistor 1.25 mv battery lowv comparator (bat_lowv) v batlv_fall battery lowv falling threshold v srn falling 2.4 2.5 2.6 v v batlv_rhyst battery lowv rising hysteresis v srn rising 200 mv i batlv battery lowv charge current limit 10m ? current sensing resistor 0.5 a thermal shutdown comparator (tshut) t shut thermal shutdown rising temperature temperature rising 155 c t shut_hys thermal shutdown hysteresis, falling temperature falling 20 c ilim comparator v ilim_fall ilim as ce falling threshold v ilim falling 60 75 90 mv v ilim_rise ilim as ce rising threshold v ilim rising 90 105 120 mv logic input (sda, scl) v in_ lo input low threshold 0.8 v v in_ hi input high threshold 2.1 v i in_ leak input bias current v = 7 v C 1 1 a logic output open drain ( acok, sda, ifault, cmpout) v out_ lo output saturation voltage 5 ma drain current 500 mv i out_ leak leakage current v = 7 v C 1 1 a analog input (acdet, ilim) i in_ leak input bias current v = 7 v C 1 1 a analog input (cmpin has 50k series resistor and 2000k pull down resistor) i in_leak input bias current v = 7 v 1 3.5 7 a pwm oscillator f sw pwm switching frequency chargeoption() bit [9] = 0 (default) 600 750 900 khz f sw+ pwm increase frequency chargeoption() bit [10:9] = 11 665 885 1100 khz f sw C pwm decrease frequency chargeoption() bit [10:9] = 01 465 615 765 khz pwm high side driver (hidrv) r ds_hi_on high side driver (hsd) turn-on resistance v btst C v ph = 5.5 v, i = 10ma 12 20 r ds_hi_off high side driver turn-off resistance v btst C v ph = 5.5 v, i = 10ma 0.65 1.3 v btst_refresh bootstrap refresh comparator threshold voltage v btst C v ph when low side refresh pulse is requested 3.85 4.3 4.7 v pwm low side driver (lodrv) r ds_lo_on low side driver (lsd) turn-on resistance v regn = 6 v, i = 10 ma 15 25 r ds_lo_off low side driver turn-off resistance v regn = 6 v, i = 10 ma 0.9 1.4 pwm driver timing t low_high driver dead time from low side to high side 20 ns t high_low driver dead time from high side to low side 20 ns internal soft start i step soft start step size in ccm mode, 10m current sense resistor 64 ma t step soft start step time in ccm mode, 10m current sense resistor 240 s independent comparator (2) v ic_ref1 comparator reference chargeoption() bit [4] = 0, rising edge (default) 0.585 0.6 0.615 v v ic_ref2 comparator reference chargeoption() bit [4] = 1, rising edge 2.375 2.4 2.425 v r s series resistor 50 k r down pull down resistor 2000 k (2) user can adjust threshold via smbus chargeoption() reg0x12. 6 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 electrical characteristics (continued) 4.5 v v (vcc) 24 v, 0 c t j 125 c, typical values are at t a = 25 c, with respect to gnd (unless otherwise noted) parameter test conditions min typ max unit smbus timing characteristics t r sclk/sdata rise time 1 s t f sclk/sdata fall time 300 ns t w(h) sclk pulse width high 4 50 s t w(l) sclk pulse width low 4.7 s t su(sta) setup time for start condition 4.7 s start condition hold time after which first clock t h(sta) 4 s pulse is generated t su(dat) data setup time 250 ns t h(dat) data hold time 300 ns t su(stop) setup time for stop condition 4 s t (buf) bus free time between start and stop condition 4.7 s f s(cl) clock frequency 10 100 khz host communication failure t timeout smbus bus release timeout (3) 25 35 ms t boot deglitch for watchdog reset signal 10 ms watchdog timeout period, chargeoption() t wdi 35 44 53 s bit [14:13] = 01 (4) watchdog timeout period, chargeoption() t wdi 70 88 105 s bit [14:13] = 10 (4) watchdog timeout period, chargeoption() t wdi 140 175 210 s bit [14:13] = 11 (4) (default) (3) devices participating in a transfer timeout when any clock low exceeds the 25ms minimum timeout period. devices that have detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. both a master and a slave must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). (4) user can adjust threshold via smbus chargeoption() reg0x12. figure 2. smbus communication timing waveforms ? 2010 C 2011, texas instruments incorporated submit documentation feedback 7 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com typical characteristics table 1. table of graphs figure no. vcc, acdet, regn and acok power up (bq24707) figure 3 charge enable by ilim figure 4 current soft-start figure 5 charge disable by ilim figure 6 continuous conduction mode switching waveforms figure 7 cycle-by-cycle synchronous to non-synchronous figure 8 100% duty and refresh pulse figure 9 system load transient (input dpm) figure 10 battery insertion figure 11 battery to ground short protection figure 12 battery to ground short transition figure 13 efficiency vs output current figure 14 ch1: vcc, 10v/div, ch2: acdet, 2v/div, ch3: acok, 5v/div, ch2: ilim, 1v/div, ch4: inductor current, 1a/div, 10ms/div ch4: regn, 5v/div, 200ms/div figure 3. vcc, acdet, regn and acok power up figure 4. charge enable by ilim (bq24707) ch1: phase, 10v/div, ch2: vin, 10v/div, ch3: lodrv, 5v/div, ch2: ilim, 1v/div, ch4: inductor current, 1a/div, 4us/div ch4: inductor current, 2a/div, 2ms/div figure 5. current soft-start figure 6. charge disable by ilim 8 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 ch1: hidrv, 10v/div, ch2: lodrv, 5v/div, ch3: phase, 10v/div, ch1: hidrv, 10v/div, ch2: lodrv, 5v/div, ch3: phase, 10v/div, ch4: inductor current, 1a/div, 400ns/div ch4: inductor current, 2a/div, 400ns/div figure 7. continuous conduction mode switching figure 8. cycle-by-cycle synchronous to waveforms non-synchronous ch2: battery current, 2a/div, ch3: adapter current, 2a/div, ch4: ch1: phase, 10v/div, ch2: lodrv, 5v/div, ch4: inductor current, system load current, 2a/div, 100us/div 2a/div, 4us/div figure 9. 100% duty and refresh pulse figure 10. system load transient (input dpm) ch1: phase, 20v/div, ch2: battery voltage, 5v/div, ch3: lodrv, ch1: phase, 20v/div, ch2: lodrv, 10v/div, ch3: battery voltage, 10v/div, ch4: inductor current, 2a/div, 400us/div 5v/div, ch4: inductor current, 2a/div, 2ms/div figure 11. battery insertion figure 12. battery to ground short protection ? 2010 C 2011, texas instruments incorporated submit documentation feedback 9 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com ch1: phase, 20v/div, ch2: lodrv, 10v/div, ch3: battery voltage, 5v/div, ch4: inductor current, 2a/div, 4us/div figure 13. battery to ground short transition figure 14. efficiency vs output current pin functions C 20-pin qfn pin description no. name input current sense resistor negative input. place an optional 0.1 f ceramic capacitor from acn to gnd for 1 acn common-mode filtering. place a 0.1 f ceramic capacitor from acn to acp to provide differential mode filtering. input current sense resistor positive input. place a 0.1 f ceramic capacitor from acp to gnd for common-mode 2 acp filtering. place a 0.1 f ceramic capacitor from acn to acp to provide differential-mode filtering. open-drain output of independent comparator. place a 10k pull-up resistor from cmpout to pull-up supply rail. 3 cmpout internal reference is 0.6v or 2.4v, selectable by smbus command chargeoption(). when cmpin is above the internal reference, cmpout goes high. place a resistor between cmpin and cmpout to program hysteresis. input of independent comparator. it has one 50k ? series resistor and one 2000k ? pull-down resistor. program cmpin voltage by connecting a resistor divider from the iout pin to the cmpin pin to the gnd pin for adapter or charge 4 cmpin current comparison or from the srn pin to the cmpin pin to the gnd pin for battery voltage comparison. the internal reference is 0.6v or 2.4v, selectable by smbus command chargeoption(). when cmpin is above the internal reference, cmpout goes high. place a resistor between cmpin and cmpout to program hysteresis. ac adapter detect open drain output. it is pulled low to gnd by an internal mosfet when the voltage on the acdet pin is above 2.4v, voltage on the vcc pin is above uvlo and voltage on the vcc pin is 245mv above the 5 acok voltage on the srn pin, indicating a valid adapter is present to start charge. if any one of the above conditions cannot meet, it is pulled high to the external pull-up supply rail by an external pull-up resistor. connect a 10k pull-up resistor from the acok pin to the pull-up supply rail. adapter detection input. program the adapter valid input threshold by connecting a resistor divider from the adapter 6 acdet input to the acdet pin to the gnd pin. when the acdet pin is above 0.6v and vcc is above uvlo, regn ldo is present, acok comparator and iout are both active. buffered adapter or charge current output, selectable with smbus command chargeoption(). iout voltage is 20 times 7 iout the differential voltage across the sense resistor. place a 100pf or less ceramic decoupling capacitor from the iout pin to gnd. smbus open-drain data i/o. connect to the smbus data line from the host controller or smart battery. connect a 10k 8 sda pull-up resistor according to smbus specifications. smbus open-drain clock input. connect to the smbus clock line from the host controller or smart battery. connect a 9 scl 10k pull-up resistor according to smbus specifications. charge current limit input. program ilim voltage by connecting a resistor divider from the system reference 3.3v rail to the ilim pin to the gnd pin. the lower of the ilim voltage or dac limit voltage sets the charge current regulation limit. 10 ilim to disable control on ilim, set ilim above 1.6v. once the voltage on the ilim pin falls below 75mv, charge is disabled. charge is enabled when the ilim pin rises above 105mv. open-drain output. it is pulled low by an internal mosfet when acoc or a short circuit is detected. it is pulled 11 ifault high to the external pull-up supply rail by an external pull-up resistor in normal condition. charge current sense resistor negative input. the srn pin is for battery voltage sensing as well. connect srn pin to a 7.5 resistor first then from resistor another terminal connect a 0.1 f ceramic capacitor to gnd for common-mode 12 srn filtering and connect to current sensing resistor. connect a 0.1 f ceramic capacitor between current sensing resistor to provide differential mode filtering. see application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor. 10 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a 88 89 90 91 92 93 94 95 96 97 98 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 charge current 4-cell 16.8 v 3-cell 12.6 v 2-cell 8.4 v efficiency - % v = 20 v, f = 750 khz, l = 4.7 h i m
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 pin functions C 20-pin qfn (continued) pin description no. name charge current sense resistor positive input. connect srp pin to a 10 resistor first then from resistor another terminal connect to current sensing resistor. connect a 0.1 f ceramic capacitor between current sensing resistor to 13 srp provide differential mode filtering. see application information about negative output voltage protection for hard shorts on battery to ground or battery reverse connection by adding small resistor. ic ground. on pcb layout, connect to the analog ground plane, and only connect to power ground plane through the 14 gnd powerpad underneath the ic. 15 lodrv low side power mosfet driver output. connect to low side n-channel mosfet gate. linear regulator output. regn is the output of the 6v linear regulator supplied from vcc. the ldo is active when the 16 regn voltage on the acdet pin is above 0.6v and voltage on vcc is above uvlo. connect a 1uf ceramic capacitor from regn to gnd. high side power mosfet driver power supply. connect a 0.047 f capacitor from btst to phase, and a bootstrap 17 btst schottky diode from regn to btst. 18 hidrv high side power mosfet driver output. connect to the high side n-channel mosfet gate. 19 phase high side power mosfet driver source. connect to the source of the high side n-channel mosfet. input supply, diode or from adapter or battery voltage. use 10 resistor and 1 f capacitor to ground as low pass 20 vcc filter to limit inrush current. exposed pad beneath the ic. analog ground and power ground star-connected only at the powerpad plane. always powerpad solder powerpad to the board, and have vias on the powerpad plane connecting to analog ground and power ground planes. it also serves as a thermal pad to dissipate the heat. ? 2010 C 2011, texas instruments incorporated submit documentation feedback 11 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com functional block diagram figure 15. functional block diagram for bq24707 and bq24707a 12 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a uvlo wakeup 3.75v 0.6v en_regn 2.4v acok_drv 20x vref_iac 20x vref_ichg vref_vreg fbo eai eao rampfrequency ** 200mv 4ma in batovp smbus interface chargeoption() chargecurrent() chargevoltage() inputcurrent() manufactureid() deviceid() 15 14 19 18 17 7 13 12 5 6 20 2 1 8 9 3 10ua regn ldo regn ldo vfb batovp vfb 104%vref_vreg vcc srn+245mv vcc-srn chg_ucp 5mv srp-srn chg_ocp srp-srn 60mv/90mv/120mv bat_lowv 2.5vsrn tshut tj 155 ? c refresh 4.3v btst-ph 1x 10 vcc acdet acok iout acp acn ilim srp srnsda scl gnd lodrv regn phase hidrv btst cmpout cmpin bq24707 and bq24707a block diagram ** threshold or deglitch time is adjustable by chargeoption() type iii compensation acgood vcc_srn ce ilim 105mv watchdog timeout en_regn en_chrg hsonlson driver logic ifault_hi acp-ph 700mv ** acoc acp-acn 1.66xvref_iac ** mux 4 1.3s rising deglitch** (bq24707)1.2ms rising deglitch** (bq24707a) ifault_lo ph-gnd 110mv light_load 1.25mv srp-srn pwm watchdog timer 175s ** watchdog timer 175s ** dac_valid charge_inhibit acok_drv 16 11 ifault ifault 0.6v ** cmpout_drv 50k 2000k iout_sel dac_valid charge_inhibit vref_vreg vref_ichg vref_iac iout_sel wakeup fast_dpm acp-acn 1.08xvref_iac
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 detailed description smbus interface the ic operates as a slave, receiving control inputs from the embedded controller host through the smbus interface. the ic uses a simplified subset of the commands documented in system management bus specification v1.1, which can be downloaded from www.smbus.org . the ic uses the smbus read-word and write-word protocols (see figure 16 ) to communicate with the smart battery. the ic performs only as a smbus slave device with address 0b00010010 (0x12h) and does not initiate communication on the bus. in addition, the ic has two identification registers a 16-bit device id register (0xffh) and a 16-bit manufacturer id register (0xfeh). smbus communication is enabled with the following conditions: ? v vcc is above uvlo; ? v acdet is above 0.6v; the data (sda) and clock (scl) pins have schmitt-trigger inputs that can accommodate slow edges. choose pull-up resistors (10k ? ) for sda and scl to achieve rise times according to the smbus specifications. communication starts when the master signals a start condition, which is a high-to-low transition on sda, while scl is high. when the master has finished communicating, the master issues a stop condition, which is a low-to-high transition on sda, while scl is high. the bus is then free for another transmission. figure 17 and figure 18 show the timing diagrams for signals on the smbus interface. the address byte, command byte, and data bytes are transmitted between the start and stop conditions. the sda state changes only while scl is low, except for the start and stop conditions. data is transmitted in 8-bit bytes and is sampled on the rising edge of scl. nine clock cycles are required to transfer each byte in or out of the ic because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. the ic supports the charger commands as described in table 2 . figure 16. smbus write-word and read-word protocols ? 2010 C 2011, texas instruments incorporated submit documentation feedback 13 product folder link(s): bq24707 bq24707a s slave address w ack command byte ack low data byte ack high data byte ack p 7 bits 1b 1b 8 bits 1b 8 bits 1b 8 bits 1b msb lsb 0 0 msb lsb 0 msb lsb 0 msb lsb 0 preset to 0b0001001 chargecurrent() = 0x14h d7 d0 d15 d8 chargevoltage() = 0x15h inputcurrent() = 0x3fh chargeoption() = 0x12h a) write-word format s slave address w ack command byte ack s slave address r ack low data byte ack high data byte nack p 7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits 1b 8 bits 1b msb lsb 0 0 msb lsb 0 msb lsb 1 0 msb lsb 0 msb lsb 1 preset to 0b0001001 deviceid() = 0xffh preset to d7 d0 d15 d8 manufactureid() = 0xfeh 0b0001001chargecurrent() = 0x14h chargevoltage() = 0x15h inputcurrent() = 0x3fh chargeoption() = 0x12h legend: s = start condition or repeated start condition p = stop condition ack = acknowledge (logic-low) nack = not acknowledge (logic-high) w = write bit (logic-low) r = read bit (logic-high) b) read-word format master to slave slave to master
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com figure 17. smbus write timing figure 18. smbus read timing battery-charger commands the ic supports six battery-charger commands that use either write-word or read-word protocols, as summarized in table 2 . manufacturerid() and deviceid() can be used to identify the ic. the manufacturerid() command always returns 0x0040h and the deviceid() command always returns 0x000ah. table 2. battery charger command summary register address register name read/write description por state 0x12h chargeoption() read or write charger options control 0x7904h 0x14h chargecurrent() read or write 7-bit charge current setting 0x0000h 0x15h chargevoltage() read or write 11-bit charge voltage setting 0x0000h 0x3fh inputcurrent() read or write 6-bit input current setting 0x1000h 0xfeh manufacturerid() read only manufacturer id 0x0040h 0xffh deviceid() read only device id 0x000ah 14 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a a = start condition e = slave pulls smbdata line low i = acknowledge clock pulse b = msb of address clocked into slave f = acknowledge bit clocked into master j = stop condition c = lsb of address clocked into sla ve g = msb of data clocked into master k = new start condition d = r/w bit clocked into slave h = lsb of data clocked into master a b c d e f g h i j k t low t high
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 setting charger options by writing chargeoption() command (0x12h or 0b00010010), the ic allows users to change several charger options after por (power on reset) as shown in table 3 . table 3. charge options register (0x12h) bit bit name description [15] acok deglitch time adjust acok deglitch time. adjust 0: acok deglitch time 1.3s for bq24707, 1.2ms for bq24707a < default at por > 1: acok deglitch time set to minimum ( < 50 s). to change this option, vcc pin voltage must be above uvlo and acdet pin voltage must be above 0.6v to enable ic smbus communication and set this bit to 1 to disable the acok deglitch timer. after por the bit default value is 0 and acok deglitch time is 1.3s for bq24707 and 1.2ms for bq24707a. [14:13] watchdog timer set maximum delay between consecutive smbus write charge voltage or charge current command. the adjust charge is suspended if the ic does not receive write charge voltage or write charge current command within the watchdog time period and watchdog timer is enabled. the charge is resumed after receive write charge voltage or write charge current command when watchdog timer expires and charge suspends. 00: disable watchdog timer 01: enabled, 44 sec 10: enabled, 88 sec 11: enable watchdog timer (175s) < default at por > [12:11] not in use 11 at por [10] emi switching 0: reduce pwm switching frequency by 18% < default at por > frequency adjust 1: increase pwm switching frequency by 18% [9] emi switching 0: disable adjust pwm switching frequency < default at por > frequency enable 1: enable adjust pwm switching frequency [8:7] ifault_hi short circuit protection high side mosfet voltage drop comparator threshold. comparator 00: 300mv threshold adjust 01: 500mv 10: 700mv < default at por > 11: 900mv [6] not in use 0 at por [5] iout selection 0: iout is the 20x adapter current amplifier output < default at por > 1: iout is the 20x charge current amplifier output [4] comparator 0: 0.6v < default at por > threshold adjust 1: 2.4v [3] not in use 0 at por [2:1] acoc threshold 00: disable acoc adjust 01: 1.33x of input current regulation limit 10: 1.66x of input current regulation limit < default at por > 11: 2.22x of input current regulation limit [0] charge inhibit 0: enable charge < default at por > 1: inhibit charge setting the charge current to set the charge current, write a 16-bit chargecurrent() command (0x14h or 0b00010100) using the data format listed in table 4 . with a 10m ? sense resistor, the ic provides a charge current range of 128ma to 8.128a, with 64ma step resolution. sending chargecurrent() below 128ma or above 8.128a clears the register and terminates charging. upon por, charge current is 0a. a 0.1 f capacitor between srp and srn for differential mode filtering, 0.1 f capacitor between srn and ground for common mode filtering, and an optional 0.1 f capacitor between srp and ground for common mode filtering is recommended. meanwhile, the capacitance on srp should not be higher than 0.1 f in order to properly sense the voltage across srp and srn for cycle-by-cycle under-current and over-current detection. the srp and srn pins are used to sense r sr with a default value of 10m . however, resistors of other values ? 2010 C 2011, texas instruments incorporated submit documentation feedback 15 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com can also be used. with a larger sense resistor comes a larger sense voltage, and higher regulation accuracy; but, at the expense of higher conduction loss. if the current sensing resistor value is too high, it may trig over current protection threshold due to the current ripple voltage being too high. in such a case either a higher inductance value or a lower current sensing resistor value should be used to limit the current ripple voltage level. a current sensing resistor value of no more than 20m is suggested. to provide secondary protection, the ic has an ilim pin with which the user can program the maximum allowed charge current. internal charge current limit is the lower one between the voltage set by chargecurrent(), and voltage on the ilim pin. to disable this function, the user can pull ilim above 1.6v, which is the maximum charge current regulation limit. the following equation shows the voltage should add on the ilim pin with respect to the preferred charge current limit: (1) table 4. charge current register (0x14h), using 10m sense resistor bit bit name description 0 C not used. 1 C not used. 2 C not used. 3 C not used. 4 C not used. 5 C not used. 6 charge current, dacichg 0 0 = adds 0ma of charger current. 1 = adds 64ma of charger current. 7 charge current, dacichg 1 0 = adds 0ma of charger current. 1 = adds 128ma of charger current. 8 charge current, dacichg 2 0 = adds 0ma of charger current. 1 = adds 256ma of charger current. 9 charge current, dacichg 3 0 = adds 0ma of charger current. 1 = adds 512ma of charger current. 10 charge current, dacichg 4 0 = adds 0ma of charger current. 1 = adds 1024ma of charger current. 11 charge current, dacichg 5 0 = adds 0ma of charger current. 1 = adds 2048ma of charger current. 12 charge current, dacichg 6 0 = adds 0ma of charger current. 1 = adds 4096ma of charger current. 13 C not used. 14 C not used. 15 C not used. setting the charge voltage to set the output charge regulation voltage, write a 16bit chargevoltage() command (0x15h or 0b00010101) using the data format listed in table 5 . the ic provides a charge voltage range from 1.024v to 19.200v, with 16mv step resolution. sending chargevoltage() below 1.024v or above 19.2v clears the register and terminates charging. upon por, the charge voltage limit is 0v. the srn pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, and directly place a decoupling capacitor (0.1 f recommended) as close to the ic as possible to decouple high frequency noise. table 5. charge voltage register (0x15h) bit bit name description 0 - not used. 1 - not used. 2 - not used. 3 - not used. 16 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a ( ) ilim srp srn chg sr v = 20 v v = 20 i r -
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 table 5. charge voltage register (0x15h) (continued) bit bit name description 4 charge voltage, dacv 0 0 = adds 0mv of charger voltage. 1 = adds 16mv of charger voltage. 5 charge voltage, dacv 1 0 = adds 0mv of charger voltage. 1 = adds 32mv of charger voltage. 6 charge voltage, dacv 2 0 = adds 0mv of charger voltage. 1 = adds 64mv of charger voltage. 7 charge voltage, dacv 3 0 = adds 0mv of charger voltage. 1 = adds 128mv of charger voltage. 8 charge voltage, dacv 4 0 = adds 0mv of charger voltage. 1 = adds 256mv of charger voltage. 9 charge voltage, dacv 5 0 = adds 0mv of charger voltage. 1 = adds 512mv of charger voltage. 10 charge voltage, dacv 6 0 = adds 0mv of charger voltage. 1 = adds 1024mv of charger voltage. 11 charge voltage, dacv 7 0 = adds 0mv of charger voltage. 1 = adds 2048mv of charger voltage. 12 charge voltage, dacv 8 0 = adds 0mv of charger voltage. 1 = adds 4096mv of charger voltage. 13 charge voltage, dacv 9 0 = adds 0mv of charger voltage. 1 = adds 8192mv of charger voltage. 14 charge voltage, dacv 10 0 = adds 0mv of charger voltage. 1 = adds 16384mv of charger voltage. 15 - not used. setting input current system current normally fluctuates as portions of the system are powered up or put to sleep. with the input current limit, the output-current requirement of the ac wall adapter can be lowered, reducing system cost. the total input current, from a wall cube or other dc source, is the sum of the system supply current and the current required by the charger. when the input current exceeds the set input current limit, the ic decreases the charge current to provide priority to system load current. as the system current rises, the available charge current drops linearly to zero. thereafter, all input current goes to system load and input current increases. during dpm regulation, the total input current is the sum of the device supply current i bias , the charger input current, and the system load current i load , and can be estimated as follows: (2) where is the efficiency of the charger buck converter (typically 85% to 95%). to set the input current limit, write a 16-bit inputcurrent() command (0x3fh or 0b00111111) using the data format listed in table 6 . when using a 10m ? sense resistor, the ic provides an input-current limit range of 128ma to 8.064a, with 128ma resolution. an input current limit set to no less than 512ma is suggested. sending inputcurrent() below 128ma or above 8.064a clears the register and terminates charging. upon por, the default input current limit is 4096ma. the acp and acn pins are used to sense r ac with a default value of 10m . however, resistors of other values can also be used. with a larger sense resistor, comes a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss. instead of using the internal dpm loop, the user can build up an external input current regulation loop and have the feedback signal on ilim. to disable the internal dpm loop, set the input current limit register value to a maximum 8.064a or a value much higher than the external dpm set point. ? 2010 C 2011, texas instruments incorporated submit documentation feedback 17 product folder link(s): bq24707 bq24707a battery battery input load bias in i v i = i + + i v ? ?
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com if input current rises above 108% of the input current limit set point, the charger shuts down immediately to let the input current fall fast. after stopping charge, the charger soft restarts to charge the battery if the adapter still has power left to charge the battery. this prevents overloading the adapter to crash when system has a high and fast loading transient. the wait time between shut down and restart charging is a natural response time of the input current limit loop. table 6. input current register (0x3fh), using 10m sense resistor bit bit name description 0 C not used. 1 C not used. 2 C not used. 3 C not used. 4 C not used. 5 C not used. 6 C not used. 7 input current, daciin 0 0 = adds 0ma of input current. 1 = adds 128ma of input current. 8 input current, daciin 1 0 = adds 0ma of input current. 1 = adds 256ma of input current. 9 input current, daciin 2 0 = adds 0ma of input current. 1 = adds 512ma of input current. 10 input current, daciin 3 0 = adds 0ma of input current. 1 = adds 1024ma of input current. 11 input current, daciin 4 0 = adds 0ma of input current. 1 = adds 2048ma of input current. 12 input current, daciin 5 0 = adds 0ma of input current. 1 = adds 4096ma of input current. 13 C not used. 14 C not used. 15 C not used. adapter detect and acok output the ic uses an acok comparator to determine the source of power on the vcc pin, either from the battery or adapter. an external resistor voltage divider attenuates the adapter voltage before it goes to acdet. the adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage but lower than the maximum allowed adapter voltage. the open drain acok output requires an external pull-up resistor to the system digital rail for a high level. it can be pulled to ground under the following conditions: ? v vcc > uvlo; ? 2.4v < v acdet (not in low input voltage condition); ? v vcc C v srn > 245mv (not in sleep mode); the default delay is 1.3s for bq24707 and 1.2ms for bq24707a after acdet has valid voltage to make acok pull low. it can be reduced by a smbus command (chargeoption() bit[15] = 0 acok delay 1.3s for bq24707 and 1.2ms for bq24707a, bit[15] = 1 acok no delay). to change this option, the vcc pin voltage must be above uvlo and the acdet pin voltage must be above 0.6v to enable ic smbus communication and set chargeoption() bit[15] to 1 to disable the acok deglitch timer. enable and disable charging in charge mode, the following conditions have to be valid to start charge: ? charge is enabled via smbus (chargeoption() bit [0] = 0, default is 0, charge enabled); ? ilim pin voltage higher than 105mv; ? all three regulation limit dacs have a valid value programmed; 18 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 ? acok is valid (see the adapter detect and acok output section for details); ? v srn does not exceed batovp threshold; ? ic temperature does not exceed tshut threshold; ? not in acoc condition (see the input over current protection (acoc) section for details); one of the following conditions stops on-going charging: ? charge is inhibited via smbus (chargeoption() bit[0] = 1); ? ilim pin voltage lower than 75mv; ? one of three regulation limit dacs is set to 0 or out of range; ? acok is pulled high (see the adapter detect and acok output section for details); ? v srn exceeds batovp threshold; ? tshut ic temperature threshold is reached; ? acoc is detected (see the input over current protection (acoc) section for details); ? short circuit is detected (see the inductor short, mosfet short protection section for details); ? watchdog timer expires if watchdog timer is enabled (see the charger timeout section for details); automatic internal soft-start charger current every time charge is enabled, the charger automatically applies soft-start on charge current to avoid any overshoot or stress on the output capacitors or the power converter. the charge current starts at 128ma, and the step size is 64ma in ccm mode for a 10m current sensing resistor. each step lasts around 240 s in ccm mode, until it reaches the programmed charge current limit. no external components are needed for this function. during dcm mode, the soft-start current step size is larger and each step lasts for a longer time period due to the intrinsic slow response of dcm mode. high accuracy current sense amplifier as an industry standard, a high accuracy current sense amplifier (csa) is used to monitor the input current or the charge current, selectable via smbus (chargeoption() bit[5] = 0 selects the input current, bit[5] = 1 selects the charge current) by the host. the csa senses voltage across the sense resistor by a factor of 20 through the iout pin. once vcc is above uvlo and acdet is above 0.6v, csa turns on and the iout output becomes valid. to lower the voltage on current monitoring, a resistor divider from iout to gnd can be used and accuracy over temperature can still be achieved. a 100pf capacitor connected on the output is recommended for decoupling high-frequency noise. an additional rc filter is optional, if additional filtering is desired. note that adding filtering also adds additional response delay. charge timeout the ic includes a watchdog timer to terminate charging if the charger does not receive a write chargevoltage() or write chargecurrent() command within 175s (adjustable via chargeoption() command). if a watchdog timeout occurs all register values stay unchanged but charge is suspended. write chargevoltage() or write chargecurrent() commands must be re-sent to reset the watchdog timer and resume charging. the watchdog timer can be disabled, or set to 44s, 88s, or 175s via a smbus command (chargeoption() bit[14:13]). after watchdog timeout write chargeoption() bit[14:13] to disable the watchdog timer also resume charging. converter operation the synchronous buck pwm converter uses a fixed frequency voltage mode control scheme and internal type iii compensation network. the lc output filter generates the following characteristic resonant frequency: (3) the resonant frequency f o is used to determine the compensation to ensure there is sufficient phase margin and gain margin for the target bandwidth. the lc output filter should be selected to generate a resonant frequency of 10 C 20 khz nominal for the best performance. the suggested component values per charge current with a 750khz default switching frequency is shown in table 7 . ? 2010 C 2011, texas instruments incorporated submit documentation feedback 19 product folder link(s): bq24707 bq24707a o o o 1 = 2 l c p |
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. see the manufacturer's data sheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. table 7. suggested component values per charge current with a default 750khz switching frequency charge current 2a 3a 4a 6a 8a output inductor lo ( h) 6.8 or 8.2 5.6 or 6.8 3.3 or 4.7 3.3 2.2 output capacitor co ( f) 20 20 20 30 40 sense resistor (m ) 10 10 10 10 10 the ic has three loops of regulation: input current, charge current, and charge voltage. the three loops are brought together internally at the error amplifier. the maximum voltage of the three loops appears at the output of the error amplifier eao (see figure 15 ). an internal saw-tooth ramp is compared to the internal error control signal eao to vary the duty-cycle of the converter. the ramp has an offset of 200mv in order to allow 0% duty-cycle. when the battery charge voltage approaches the input voltage, the eao signal is allowed to exceed the saw-tooth ramp peak in order to get a 100% duty-cycle. if voltage across the btst and phase pins falls below 4.3v, a refresh cycle starts and the low-side n-channel power mosfet is turned on to recharge the btst capacitor. it can achieve a duty-cycle of up to 99.5%. continuous conduction mode (ccm) with sufficient charge current the ic inductor current never crosses zero, which is defined as continuous conduction mode. the controller starts a new cycle with ramp coming up from 200mv. as long as eao voltage is above the ramp voltage, the high-side mosfet (hsfet) stays on. when the ramp voltage exceeds eao voltage, the hsfet turns off and the low-side mosfet (lsfet) turns on. at the end of the cycle, the ramp gets reset and the lsfet turns off, ready for the next cycle. there is always break-before-make logic during the transition to prevent cross-conduction and shoot-through. during the dead time when both mosfets are off, the body-diode of the low-side power mosfet conducts the inductor current. during ccm mode, the inductor current is always flowing and creates a fixed two-pole system. having the lsfet turn-on keeps the power dissipation low and allows safely charging at high currents. discontinuous conduction mode (dcm) during the hsfet off time when lsfet is on, the inductor current decreases. if the current goes to zero, the converter enters discontinuous conduction mode. every cycle, when the voltage across srp and srn falls below 5mv (0.5a on 10m ), the under-current-protection comparator (ucp) turns off lsfet to avoid negative inductor current, which may boost the system via the body diode of hsfet. during the dcm mode the loop response automatically changes. it changes to a single pole system and the pole is proportional to the load current. both ccm and dcm are synchronous operation with lsfet turn-on every clock cycle. if the average charge current goes below 125ma on 10m current sensing resistor or the battery voltage falls below 2.5v, the lsfet keeps turn-off. the battery charger operates in non-synchronous mode and the current flows through the lsfet body diode. during non-synchronous operation, the lsfet turns on only for refreshing pulse to charge btst capacitor. if the average charge current goes above 250ma on 10m current sensing resistor, the lsfet exits non-synchronous mode and enters synchronous mode to reduce lsfet power loss. input over current protection (acoc) the ic cannot maintain the input current level if the charge current has been already reduced to zero. after the system current continues increasing to the 1.66x of input current dac set point (with 2.5ms blank out time), ifault is pulled to low and the charge is disabled for 1.3s and will soft start again for charge if acoc condition goes away. if such failure is detected seven times in 90 seconds, charge will be latched off and an adapter removal and system shut down (make acdet < 0.6v to reset ic) is required to start charge again. after 90 seconds, the failure counter will be reset to zero to prevent latch off. 20 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 the acoc function can be disabled or the threshold can be set to 1.33x, 1.66x or 2.22x of input dpm current via smbus command (chargeoption() bit [2:1]). charge over current protection (chgocp) the ic has a cycle-by-cycle peak over-current protection. it monitors the voltage across srp and srn, and prevents the current from exceeding of the threshold based on the dac charge current set point. the high-side gate drive turns off for the rest of the cycle when the over-current is detected, and resumes when the next cycle starts. the charge ocp threshold is automatically set to 6a, 9a, and 12a on a 10m current sensing resistor based on charge current register value. this prevents the threshold to be too high which is not safe or too low which can be triggered in normal operation. proper inductance should be selected to prevent ocp triggered in normal operation due to high inductor current ripple. battery over voltage protection (batovp) the ic will not allow the high-side and low-side fet to turn-on when the battery voltage at srn exceeds 104% of the regulation voltage set-point. if batovp last over 30ms, charger is completely disabled. this allows quick response to an over-voltage condition C such as occurs when the load is removed or the battery is disconnected. a 4ma current sink from srn to gnd is on only during batovp and allows discharging the stored output inductor energy that is transferred to the output capacitors. some battery pack gas gauges will set the chargevoltage() and chargecurrent() registers to 0v and 0a after the battery pack is fully charged. if the chargevoltage() register is set to 0v, the bq24707 triggers batovp, and the 4ma current discharges the battery pack. the recommendation for bq24707 is to set the chargevoltage() register to full scale charge voltage (12.592v for 3s battery for example) after the battery is fully charged. the bq24707a will not trigger batovp, and there is no 4ma current to discharge the battery pack if the chargevoltage() register is set 0v. the recommendation for bq24707a is to set the chargevoltage() register to 0v after the battery is fullycharged. battery shorted to ground (batlowv) the ic will disable charge for 1ms if the battery voltage on srn falls below 2.5v. after 1ms reset, the charge is resumed with soft-start if all the enable conditions in the enable and disable charging sections are satisfied. this prevents any overshoot current in inductor which can saturate inductor and may damage the mosfet. the charge current is limited to 0.5a on 10m current sensing resistor when batlowv condition persists and lsfet keeps off. the lsfet turns on only for refreshing pulse to charge btst capacitor. thermal shutdown protection (tshut) the qfn package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. as added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155 c. the charger stays off until the junction temperature falls below 135 c. during thermal shut down, the regn ldo current limit is reduced to 16ma. once the temperature falls below 135 c, charge can be resumed with soft start. emi switching frequency adjust the charger switching frequency can be adjusted 18% to solve emi issue via smbus command. chargeoption() bit [9]=0 disable the frequency adjust function. to enable frequency adjust function, set chargeoption() bit[9]=1. set chargeoption() bit [10]=0 to reduce switching frequency, set bit[10]=1 to increase switching frequency. if frequency is reduced, for a fixed inductor the current ripple is increased. inductor value must be carefully selected so that it will not trig cycle-by-cycle peak over current protection even for the worst condition such as higher input voltage, 50% duty cycle, lower inductance and lower switching frequency. ? 2010 C 2011, texas instruments incorporated submit documentation feedback 21 product folder link(s): bq24707 bq24707a
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com inductor short, mosfet short protection the ic has a unique short circuit protection feature. its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across r ds(on) of the mosfets after a certain amount of blanking time. in case of mosfet short or inductor short circuit, the over current condition is sensed by two comparators and two counters will be triggered. after seven times of short circuit events, the charger will be latched off. to reset the charger from latch-off status, the ic vcc pin must be pulled down below uvlo or acdet pin must be pulled down below 0.6v. this can be achieved by removing the adapter and shut down the operation system. the low side mosfet short circuit voltage drop threshold is fixed to typical 110mv. the high side mosfet short circuit voltage drop threshold can be adjusted via smbus command. chargeoption() bit[8:7] = 00, 01, 10, 11 set the threshold 300mv, 500mv, 700mv and 900mv respectively. due to the certain amount of blanking time to prevent noise when mosfet just turns on, the cycle-by-cycle charge over-current protection may detect high current and turn off mosfet first before the short circuit protection circuit can detect short condition because the blanking time has not finished. in such a case the charge may not be able to detect shorts circuit and counter may not be able to count to seven then latch off. instead the charge may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle current peak value. however, the charger should still be safe and will not cause failure because the duty cycle is limited to a very short of time and mosfet should be still inside the safety operation area. during a soft start period, it may takes long time instead of just seven switching cycles to detect short circuit based on the same blanking time reason. independent comparator the ic has an independent comparator can be used to compare input current, charge current or battery voltage with internal reference . program cmpin voltage by connecting a resistor divider from iout pin to cmpin pin to gnd pin for adapter or charge current comparison or from srn pin to cmpin pin to gnd pin for battery voltage comparison. when cmpin is above internal reference, cmpout is pulled to external pull up rail by external pull up resistor. when cmpin is below internal reference, cmpout is pulled to gnd by internal mosfet. place a resistor between cmpin and cmpout to program hysteresis. the internal reference can be set to 0.6v or 2.4v via smbus command (chargeoption() bit[4]=0 set internal reference 0.6v, bit[4]=1 set 2.4v). there is one 50k ? series resistor r s and one 2000k ? pull down resistor r down for cmpin pin as shown in figure 19 . to get the accurate comparison set point, these two resistors must be included in the calculation. a spreadsheet calculation tool has been developed to simplify the design work. user can down load from the ti web site at www.ti.com under the ic product folder. figure 19 also shows one application circuit using this comparator for battery voltage comparison. after using the superposition principle and fill the components value into the spreadsheet the battery voltage threshold is 9.45v for rising edge and 8.99v for falling edge. figure 19. ic comparator internal circuit and application circuit 22 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a 0.6v/2.4v cmpout r down 2000k r s 50k cmpin 0.6v/2.4v cmpout r down 2000k r s 50k cmpin 0.6v r down 2000k r s 50k cmpin 3.3v v bat r hys 3010k r up 10k r top 422k r bot 30.1k cmpout 0.6v r down 2000k r s 50k cmpin 3.3v v bat r hys 3010k r up 10k r top 422k r bot 30.1k cmpout (a) internal circuit showing the series resistor and pull down resistor (b) application circuit, 9.45v rising edge and 8.99v falling edge for 3cell battery
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 table 8. component list for typical system circuit of figure 1 part designator qty description c1, c2, c3, c13, c14 5 capacitor, ceramic, 0.1 f, 25v, 10%, x7r, 0603 c4 1 capacitor, ceramic, 100pf, 25v, 10%, x7r, 0603 c5, c6 2 capacitor, ceramic, 1 f, 25v, 10%, x7r, 0603 c7 1 capacitor, ceramic, 0.047 f, 25v, 10%, x7r, 0603 c8, c9, c10, c11 4 capacitor, ceramic, 10 f, 25v, 10%, x7r, 1206 ci 1 capacitor, ceramic, 2.2 f, 25v, 10%, x7r, 1210 csys 1 capacitor, electrolytic, 220 f, 25v d1 1 diode, schottky, 30v, 200ma, sot-23, fairchild, bat54 d2 1 diode, schottky, 40v, 120ma, sod-323, nxp, rb751v40 q1, q2, q5 3 p-channel mosfet, C 30v, C 9.4a, so-8, vishay siliconix, si4435ddy q3, q4 2 n-channel mosfet, 30v, 12a, powerpak 1212-8, vishay siliconix, sis412dn l1 1 inductor, smt, 4.7 h, 5.5a, vishay dale, ihlp2525czer4r7m01 r1 1 resistor, chip, 430k ? , 1/10w, 1%, 0603 r2 1 resistor, chip, 66.5k ? , 1/10w, 1%, 0603 r3, r4, r5, r6, r10 5 resistor, chip, 10k ? , 1/10w, 1%, 0603 r7 1 resistor, chip, 316k ? , 1/10w, 1%, 0603 r8, r12 2 resistor, chip, 100k ? , 1/10w, 1%, 0603 r9 1 resistor, chip, 10 ? , 1/4w, 1%, 1206 r11 1 resistor, chip, 39.2k ? , 1/10w, 1%, 0603 r13 1 resistor, chip, 3.01m ? , 1/10w, 1%, 0603 r14 1 resistor, chip, 10 ? , 1/10w, 5%, 0603 r15 1 resistor, chip, 7.5 , 1/10w, 5%, 0603 rac, rsr 2 resistor, chip, 0.01 ? , 1/2w, 1%, 1206 ri 1 resistor, chip, 2 ? , 1/2w, 1%, 1210 u1 1 charger controller, 20 pin vqfn, ti, bq24707rgr or bq24707argr application information negative output voltage protection reversely insert the battery pack into the charger output during production or hard shorts on battery to ground will generate negative output voltage on srp and srn pin. ic internal electrostatic-discharge (esd) diodes from gnd pin to srp or srn pins and two anti-parallel (ap) diodes between srp and srn pins can be forward biased and negative current can pass through the esd diodes and ap diodes when output has negative voltage. insert two small resistors for srp and srn pins to limit the negative current level when output has negative voltage. suggest resistor value is 10 for srp pin and 7-8 for srn pin. after adding small resistors, the suggested pre-charge current is at least 192ma for a 10m current sensing resistor. inductor selection the ic has three selectable fixed switching frequencies. higher switching frequency allows the use of smaller inductor and capacitor values. inductor saturation current should be higher than the charging current (i chg ) plus half the ripple current (i ripple ): (4) the inductor ripple current depends on input voltage (v in ), duty cycle (d = v out /v in ), switching frequency (f s ) and inductance (l): (5) ? 2010 C 2011, texas instruments incorporated submit documentation feedback 23 product folder link(s): bq24707 bq24707a in ripple s v d (1 d) i = l f - sat chg ripple i i + (1/2) i 3
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com the maximum inductor ripple current happens with d = 0.5 or close to 0.5. for example, the battery charging voltage range is from 9v to 12.6v for 3-cell battery pack. for 20v adapter voltage, 10v battery voltage gives the maximum inductor ripple current. another example is 4-cell battery, the battery voltage range is from 12v to 16.8v, and 12v battery voltage gives the maximum inductor ripple current. usually inductor ripple is designed in the range of (20-40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. the ic has charge under current protection (ucp) by monitoring charging current sensing resistor cycle-by-cycle. the typical cycle-by-cycle ucp threshold is 5mv falling edge corresponding to 0.5a falling edge for a 10m charging current sensing resistor. when the average charging current is less than 125ma for a 10m charging current sensing resistor, the low side mosfet is off until btst capacitor voltage needs to refresh charge. as a result, the converter relies on low side mosfet body diode for the inductor freewheeling current. input capacitor input capacitor should have enough ripple current rating to absorb input switching ripple current. the worst case rms ripple current is half of the charging current when duty cycle is 0.5. if the converter does not operate at 50% duty cycle, then the worst case capacitor rms current occurs where the duty cycle is closest to 50% and can be estimated by equation 6 : (6) low esr ceramic capacitor such as x7r or x5r is preferred for input decoupling capacitor and should be placed to the drain of the high side mosfet and source of the low side mosfet as close as possible. voltage rating of the capacitor must be higher than normal input voltage level. 25v rating or higher capacitor is preferred for 19-20v input voltage. 10-20 f capacitance is suggested for typical of 3-4a charging current. ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the input capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high input voltages and small capacitor packages. see the manufacturer's data sheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. output capacitor output capacitor also should have enough ripple current rating to absorb output switching ripple current. the output capacitor rms current is given: (7) the ic has internal loop compensator. to get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 khz and 20 khz. the preferred ceramic capacitor is 25v x7r or x5r for output capacitor. 10-20 f capacitance is suggested for typical of 3-4a charging current. place capacitors after charging current sensing resistor to get the best charge current regulation accuracy. ceramic capacitors show a dc-bias effect. this effect reduces the effective capacitance when a dc-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. the effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. see the manufacturer's data sheet about the performance with a dc bias voltage applied. it may be necessary to choose a higher voltage rating or nominal capacitance value in order to get the required value at the operating point. power mosfets selection two external n-channel mosfets are used for a synchronous switching battery charger. the gate drivers are internally integrated into the ic with 6v of gate drive voltage. 30v or higher voltage rating mosfets are preferred for 19-20v input voltage. figure-of-merit (fom) is usually used for selecting proper mosfet based on a tradeoff between the conduction loss and switching loss. for top side mosfet, fom is defined as the product of a mosfet's on-resistance, r ds(on) , and the gate-to-drain charge, q gd . for bottom side mosfet, fom is defined as the product of the mosfet's on-resistance, r ds(on) , and the total gate charge, q g . fom top = r ds(on) x q gd ; fom bottom = r ds(on) x q g (8) 24 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a ripple cout ripple i i = 0.29 i 2 3 ? cin chg i = i d (1 d) -
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 the lower the fom value, the lower the total power loss. usually lower r ds(on) has higher cost with the same package size. the top-side mosfet loss includes conduction loss and switching loss. it is a function of duty cycle (d=v out /v in ), charging current (i chg ), mosfet's on-resistance ? ds(on) ), input voltage (v in ), switching frequency (f s ), turn on time (t on ) and turn off time (t off ): (9) the first item represents the conduction loss. usually mosfet r ds(on) increases by 50% with 100 c junction temperature rise. the second term represents the switching loss. the mosfet turn-on and turn-off times are given by: (10) where q sw is the switching charge, i on is the turn-on gate driving current and i off is the turn-off gate driving current. if the switching charge is not given in mosfet datasheet, it can be estimated by gate-to-drain charge (q gd ) and gate-to-source charge (q gs ): (11) gate driving current can be estimated by regn voltage (v regn ), mosfet plateau voltage (v plt ), total turn-on gate resistance (r on ) and turn-off gate resistance (r off ) of the gate driver: (12) the conduction loss of the bottom-side mosfet is calculated with the following equation when it operates in synchronous continuous conduction mode: (13) when charger operates in non-synchronous mode, the bottom-side mosfet is off. as a result all the freewheeling current goes through the body-diode of the bottom-side mosfet. the body diode power loss depends on its forward voltage drop (v f ), non-synchronous mode charging current (i nonsync ), and duty cycle (d). p d = v f x i nonsync x (1 - d) (14) the maximum charging current in non-synchronous mode can be up to 0.25a for a 10m charging current sensing resistor or 0.5a if battery voltage is below 2.5v. the minimum duty cycle happens at lowest battery voltage. choose the bottom-side mosfet with either an internal schottky or body diode capable of carrying the maximum non-synchronous mode charging current. input filter design during adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. the voltage spike at vcc pin maybe beyond ic maximum voltage rating and damage ic. the input filter must be carefully designed and tested to prevent over voltage event on vcc pin. there are several methods to damping or limit the over voltage spike during adapter hot plug-in. an electrolytic capacitor with high esr as an input capacitor can damp the over voltage spike well below the ic maximum pin voltage rating. a high current capability tvs zener diode can also limit the over voltage level to an ic safe level. however these two solutions may not have low cost or small size. a cost effective and small size solution is shown in figure 20 . the r1 and c1 are composed of a damping rc network to damp the hot plug-in oscillation. as a result the over voltage spike is limited to a safe level. d1 is used for reverse voltage protection for vcc pin. c2 is vcc pin decoupling capacitor and it should be place to vcc pin as close as possible. c2 value should be less than c1 value so r1 can dominant the equivalent esr value to get enough damping effect. r2 is used to limit inrush current of d1 to prevent d1 getting damage when adapter hot plug-in. r2 and c2 should have 10us time constant to limit the dv/dt on vcc pin to reduce inrush current when adapter hot plug in. r1 has high inrush current. r1 package must be sized enough to handle inrush current power loss according to resistor manufacturer s datasheet. the filter components value always need to be verified with real application and minor adjustments may need to fit in the real application circuit. ? 2010 C 2011, texas instruments incorporated submit documentation feedback 25 product folder link(s): bq24707 bq24707a 2 top chg ds(on) in chg on off s 1 p = d i r + v i (t + t ) 2 f regn plt plt on off on off v - v v i = , i = r r - 2 bottom chg ds(on) p = (1 d) i r sw gd gs 1 q = q + q 2 sw sw on off on off q q t = , t = i i
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com figure 20. input filter ic design guideline the ic has a unique short circuit protection feature. its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across rdson of the mosfets after a certain amount of blanking time. in case of mosfet short or inductor short circuit, the over current condition is sensed by two comparators and two counters will be triggered. after seven times of short circuit events, the charger will be latched off. the way to reset the charger from latch-off status is reconnect adapter. figure 21 shows the ic short circuit protection block diagram. figure 21. block diagram of ic short circuit protection in normal operation, low side mosfet current is from source to drain which generates negative voltage drop when it turns on, as a result the over current comparator can not be triggered. when high side switch short circuit or inductor short circuit happens, the large current of low side mosfet is from drain to source and can trig low side switch over current comparator. ic senses low side switch voltage drop by phase pin and gnd pin. the high-side fet short is detected by monitoring the voltage drop between acp and phase. as a result, it not only monitors the high side switch voltage drop, but also the adapter sensing resistor voltage drop and pcb trace voltage drop from acn terminal of rac to charger high side switch drain. usually, there is a long trance between input sensing resistor and charger converting input, a careful layout will minimize the trace effect. 26 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a phase battery adapter acp acn r ac btst regn high-side mosfet low-side mosfet clr count to 7 adapterplug in r dc l latch offcharger scp1 scp2 comp1 comp2 r pcb c r1(2010) 2 c1 2.2f d1 c2 0.471f r2(1206) 1020 adapterconnector vcc pin
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 to prevent unintentional charger shut down in normal operation, mosfet r ds(on) selection and pcb layout is very important. figure 22 shows a need improve pcb layout example and its equivalent circuit. in this layout, system current path and charger input current path is not separated, as a result, the system current causes voltage drop in the pcb copper and is sensed by ic. the worst layout is when a system current pull point is after charger input; as a result all system current voltage drops are counted into over current protection comparator. the worst case for ic is the total system current and charger input current sum equals dpm current. when system pull more current, the charger ic try to regulate r ac current as a constant current by reducing charging current. figure 22. need improve pcb layout example figure 23 shows the optimized pcb layout example. the system current path and charge input current path is separated, as a result the ic only senses charger input current caused pcb voltage drop and minimized the possibility of unintentional charger shut down in normal operation. this also makes pcb layout easier for high system current application. figure 23. optimized pcb layout example the total voltage drop sensed by ic can be express as the following equation. v top = r ac x i dpm + r pcb x (i chrgin + (i dpm - i chrgin ) x k) + r ds(on) x i peak (15) where the r ac is the ac adapter current sensing resistance, i dpm is the dpm current set point, r pcb is the pcb trace equivalent resistance, i chrgin is the charger input current, k is the pcb factor, r ds(on) is the high side mosfet turn on resistance and i peak is the peak current of inductor. here the pcb factor k equals 0 means the best layout shown in figure 23 where the pcb trace only goes through charger input current while k equals 1 means the worst layout shown in figure 22 where the pcb trace goes through all the dpm current. the total voltage drop must below the high side short circuit protection threshold to prevent unintentional charger shut down in normal operation. the low side mosfet short circuit voltage drop threshold is fixed to typical 110mv. the high side mosfet short circuit voltage drop threshold can be adjusted via smbus command. chargeoption() bit[8:7] = 00, 01, 10, 11 set the threshold 300mv, 500mv, 700mv and 900mv respectively. for a fixed pcb layout, host should set proper short circuit protection threshold level to prevent unintentional charger shut down in normal operation. ? 2010 C 2011, texas instruments incorporated submit documentation feedback 27 product folder link(s): bq24707 bq24707a to acp to acn system current charger input current single point connection at r ac system path pcb trace charger input pcb trace r ac acp acn charger r ac r pcb i chrgin i bat i sys i dpm (a) pcb layout (b) equivalent circuit r ac to acp to acn system path pcb trace system current charger input current charger input pcb trace acp acn r ac charger r pcb i chrgin i bat i sys i dpm (a) pcb layout (b) equivalent circuit
bq24707 bq24707a slusa78b C july 2010 C revised march 2011 www.ti.com pcb layout the switching node rise and fall times should be minimized for minimum switching loss. proper layout of the components to minimize high frequency current path loop (see figure 24 ) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. here is a pcb layout priority list for proper layout. layout pcb according to this specific order is essential. 1. place input capacitor as close as possible to switching mosfet s supply and ground connections and use shortest copper trace connection. these parts should be placed on the same layer of pcb instead of on different layers and using vias to make this connection. 2. the ic should be placed close to the switching mosfet s gate terminals and keep the gate drive signal traces short for a clean mosfet drive. the ic can be placed on the other side of the pcb of switching mosfets. 3. place inductor input terminal to switching mosfet s output terminal as close as possible. minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. do not use multiple layers in parallel for this connection. minimize parasitic capacitance from this area to any other trace or plane. 4. the charging current sensing resistor should be placed right next to the inductor output. route the sense leads connected across the sensing resistor back to the ic in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see figure 25 for kelvin connection for best current accuracy). place decoupling capacitor on these traces next to the ic 5. place output capacitor next to the sensing resistor output and ground 6. output capacitor ground connections need to be tied to the same copper that connects to the input capacitor ground before connecting to system ground. 7. use single ground connection to tie charger power ground to charger analog ground. just beneath the ic use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling 8. route analog ground separately from power ground. connect analog ground and connect power ground separately. connect analog ground and power ground together using power pad as the single ground connection point. or using a 0 resistor to tie analog ground to power ground (power pad should tie to analog ground in this case if possible). 9. decoupling capacitors should be placed next to the ic pins and make trace connection as short as possible 10. it is critical that the exposed power pad on the backside of the ic package be soldered to the pcb ground. ensure that there are sufficient thermal vias directly under the ic, connecting to the ground plane on the other layers. 11. the via size and number should be enough for a given current path. see the evm design for the recommended component placement with trace and via locations. for the qfn information, see scba017 and slua271 . figure 24. high frequency current path 28 submit documentation feedback ? 2010 C 2011, texas instruments incorporated product folder link(s): bq24707 bq24707a high frequency current path l1 r1 c2 c1 gnd phase v bat bat v in
bq24707 bq24707a www.ti.com slusa78b C july 2010 C revised march 2011 figure 25. sensing resistor pcb layout revision history changes from original (july 2010) to revision a page ? changed the functional block diagram, figure 1 ................................................................................................................ 2 ? updated the description for the srn and srp pins ........................................................................................................... 10 ? deleted c12, added r14 and r15 in table 8 .................................................................................................................... 23 ? added added section: negative output voltage protection ............................................................................................... 23 changes from revision a (november 2010) to revision b page ? added features for the bq24707 and bq24707a ................................................................................................................. 1 ? added device bq24707a to this data sheet .......................................................................................................................... 1 ? added bq24707a to the ordering information table ................................................................................................ 2 ? added the comparison table ....................................................................................................................................... 2 ? added bq24707 only to the test condition of t acok_fall_deg first row .................................................................................... 5 ? added bq24707a only to the test condition of t acok_fall_deg second row ............................................................................ 5 ? added (bq24707) to the title of figure 3 ............................................................................................................................... 8 ? changed the description of the acok deglitch time adjust bit in table 3 ....................................................................... 15 ? changed the adapter detect and acok output section. included 1.3s for bq24707 and 1.2ms for bq24707a ............... 18 ? added a new paragraph in the battery over voltage protection (batovp) section ......................................................... 21 ? changed the description of item u1 in table 8 .................................................................................................................. 23 ? 2010 C 2011, texas instruments incorporated submit documentation feedback 29 product folder link(s): bq24707 bq24707a charge current direction to srp and srn pin r sns to inductor to capacitor and battery current sensing direction
package option addendum www.ti.com 16-apr-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) bq24707argrr active vqfn rgr 20 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year bq24707argrt active vqfn rgr 20 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year bq24707rgrr active vqfn rgr 20 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year BQ24707RGRT active vqfn rgr 20 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant bq24707argrr vqfn rgr 20 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 bq24707argrr vqfn rgr 20 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 bq24707argrt vqfn rgr 20 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 bq24707argrt vqfn rgr 20 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 bq24707rgrr vqfn rgr 20 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 bq24707rgrr vqfn rgr 20 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 BQ24707RGRT vqfn rgr 20 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 package materials information www.ti.com 19-may-2011 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) bq24707argrr vqfn rgr 20 3000 346.0 346.0 29.0 bq24707argrr vqfn rgr 20 3000 346.0 346.0 29.0 bq24707argrt vqfn rgr 20 250 190.5 212.7 31.8 bq24707argrt vqfn rgr 20 250 190.5 212.7 31.8 bq24707rgrr vqfn rgr 20 3000 346.0 346.0 29.0 bq24707rgrr vqfn rgr 20 3000 346.0 346.0 29.0 BQ24707RGRT vqfn rgr 20 250 190.5 212.7 31.8 package materials information www.ti.com 19-may-2011 pack materials-page 2

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